IBM’s new Telum Processor will be designed deep learning inference to enterprise workloads to help address fraud in real-time. Telum is IBM's first processor that contains on-chip acceleration for AI inferencing while a transaction is taking place.
Three years in development, the on-chip hardware acceleration is designed to help users achieve business insights at scale across banking, finance, trading, insurance applications and customer interactions.
In a media release, IBM said businesses typically apply detection techniques to catch fraud after it occurs, a process that can be time consuming and compute-intensive due to the limitations of existing technologies, particularly when fraud analysis and detection is conducted far away from mission critical transactions and data.
Because complex fraud detection often cannot be completed in real-time, a bad actor could purchase goods with a stolen credit card before the retailer is aware fraud has taken place.
Telum can help users move their thinking from a fraud detection posture to a fraud prevention posture, evolving from catching many cases of fraud today, to a potentially new era of prevention of fraud at scale, without impacting service level agreements, before the transaction is completed.
From fraud detection to prevention
The new chip features an innovative centralised design, which allows clients to leverage the full power of the AI processor for AI-specific workloads, making it ideal for financial services workloads like fraud detection, loan processing, clearing and settlement of trades, anti-money laundering and risk analysis.
Users will be positioned to enhance existing rules-based fraud detection or use machine learning, accelerate credit approval processes, improve customer service and profitability, identify which trades or transactions may fail, and propose solutions to create a more efficient settlement process.
The chip contains 8 processor cores with a deep super-scalar out-of-order instruction pipeline, running with more than 5GHz clock frequency, optimised for the demands of hetereogenous enterprise class workloads. The redesigned cache and chip-interconnection infrastructure provides 32MB cache per core, and can scale to 32 Telum chips. The dual-chip module design contains 22 billion transistors and 19 miles of wire on 17 metal layers.
